Portrait of Dejan Kostic

Dejan Kostic

Chair Professor of Internetworking, KTH Royal Institute of Technology · Wallenberg Scholar · WASP faculty · associated with the Connected Intelligence unit of RISE

Main research interests: distributed systems, machine learning, computer networks and operating systems. My group works on making computing dramatically more efficient — from network stacks that saturate 100+ Gbps links on a single CPU core, to inference platforms that aim to put large language models within everyone's reach at a fraction of today's energy cost.

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Selected work

Main publications

Full author lists and the complete record are in all publications below and in DiVA.

The KVComm pipeline: a calibration stage scores KV pairs by cross-model attention, and at test time only the selected KV pairs reach the answering model.click to enlarge
From the paper: calibration scores each KV pair by cross-model attention; at test time only the selected pairs are handed to the answering model.
ICLR·2026

KVComm: Enabling Efficient LLM Communication through Selective KV Sharing

When several LLMs collaborate on a problem, shipping natural-language text between them is wasteful. KVComm instead passes a carefully chosen subset of the key–value pairs computed during self-attention, selected via attention importance scores and a Gaussian prior. The result: 2.5–6× less computation than textual approaches, and up to 3× less communication than sending the whole KV cache.

Queue-Mem: the ASIC switch splits each packet, sends the header to the external NF processor, and buffers the payload in the output-port queue until the processed header returns, when the packet is rebuilt.click to enlarge
From the paper: payloads wait in the switch output-port queue while the headers are processed externally, then the packet is rebuilt.
USENIX NSDI·2026

Queue-Mem: Energy-Efficient Hardware Storage for Advanced Network Function Acceleration

Accelerating network functions in hardware runs into a storage wall: packets must be held somewhere while they are processed, and that memory costs both power and area. Queue-Mem is a hardware storage design that makes this far cheaper energetically, so more advanced network functions fit within the same power budget.

FAJITA pipeline: a flow manager routes packets to per-flow state blocks, and each network function prefetches its state before the processing phase.click to enlarge
From the paper: the flow manager groups packets by state block, and each NF prefetches its state before processing.
ACM CoNEXT·2024

FAJITA: Stateful Packet Processing at 100 Million pps

A commodity server running a whole chain of stateful network functions can process more than 170 million packets per second — the equivalent of 1.4 Tbps when payloads are stored in a disaggregated fashion, as in our earlier Ribosome work. This was the closing result of the ULTRA ERC project.

NetConfEval prototype: three LLM stages take high-level policies to a formal specification, high-level configuration and finally low-level device configuration, with a verifier checking each stage.click to enlarge
From the paper: three LLM stages carry high-level policy down to device configuration, with a verifier checking each step.
ACM CoNEXT·2024 ANRP Award

NetConfEval: Can LLMs Facilitate Network Configuration?

Rather than asking in the abstract whether an LLM can configure a network, NetConfEval builds a benchmark around the tasks operators actually face — translating high-level requirements, producing code that drives the network, and generating low-level configuration — and measures where today's models succeed and where they break. Recognized with an Applied Networking Research Prize.

Ribosome overview: the programmable switch sends headers to the NF packet processor and stores payloads on RDMA servers, retrieving and rejoining them on egress.click to enlarge
From the paper: headers go to the NF processor, payloads are parked on RDMA servers, and the two are rejoined on egress.
USENIX NSDI·2023

A High-Speed Stateful Packet Processing Approach for Tbps Programmable Switches

Programmable switches have the throughput for terabit-scale stateful processing but nowhere near the memory. Ribosome resolves the tension by disaggregating storage: the switch keeps what it needs to make decisions, while payloads live elsewhere — which is what later let FAJITA quote 1.4 Tbps-equivalent numbers on commodity hardware.

Top: flows from different servers are interleaved by the network before reaching the receiver. Bottom: Reframer buffers packets briefly and forwards them grouped by flow.click to enlarge
From the paper: the network interleaves flows (top); Reframer regroups them by flow before the server sees them (bottom).
USENIX NSDI·2022 Community Award

Packet Order Matters! Improving Application Performance by Deliberately Delaying Packets

A counter-intuitive result: deliberately delaying packets can improve the performance of backend servers by up to a factor of 2, because an interleaved stream wrecks locality downstream. Our Reframer buys order with a little latency, and we show three deployment scenarios where that trade is clearly worth it. Covered by KTH EECS and Ericsson.

RedN hash-lookup RDMA program: a posted chain of RECV, READ, CAS and SEND work requests in which each step rewrites the next, so the NIC walks the hash table on its own.click to enlarge
From the paper: a chain of RDMA work requests that rewrites itself — the NIC walks the hash table with no remote CPU involved.
USENIX NSDI·2022

RDMA is Turing complete, we just did not know it yet!

RDMA, as implemented in widely deployed RDMA Network Interface Cards, turns out to be Turing complete. We leverage that finding to offload real computation onto the NIC and reduce the tail latency of services running on busy servers by 35×. Picked up by TechXplore and HPCwire.

LineFS IO path across host and SmartNIC: fetching, validation, compression and transfer to the replicas overlap as a pipeline.click to enlarge
From the paper: the IO path across host and SmartNIC — fetch, validate, compress and transfer overlap instead of queuing.
ACM SOSP·2021 Best Paper

LineFS: Efficient SmartNIC Offload of a Distributed File System with Pipeline Parallelism

Building on Assise, LineFS offloads the CPU-intensive tasks of a distributed file system to a SmartNIC (BlueField-1 in our case) and pipelines them, for about 80% performance improvement across the board. Best Paper Award at SOSP '21, and news at KTH EECS.

Data Direct I/O: the network interface card DMAs incoming data straight into the last-level cache of the CPU socket rather than into DRAM.click to enlarge
From the paper: with Data Direct I/O the NIC places incoming data straight into the last-level cache rather than DRAM.
USENIX ATC·2020

Reexamining Direct Cache Access to Optimize I/O Intensive Applications for Multi-hundred-gigabit Networks

Direct Cache Access lets a NIC deliver packets into the last-level cache instead of DRAM — a design whose assumptions no longer hold at multi-hundred-gigabit rates. We reexamine DCA as it is actually implemented in Intel processors, and show how to tune it for I/O intensive applications at these speeds.

Receive Side Scaling: the NIC hashes each packet into an indirection table whose buckets are assigned to processing cores.click to enlarge
From the paper: RSS hashes packets into an indirection table of buckets — the table RSS++ rebalances at run time.
ACM CoNEXT·2019

RSS++: load and state-aware receive side scaling

RSS++ shows how load-balancing with Receive Side Scaling (RSS) — the mechanism every modern NIC already uses to spread packets across cores — can be improved for large increases in efficiency.

Traditional DPDK places the first 64 bytes of the packet — the header — in a random last-level cache slice; with CacheDirector the mbuf headroom is adjusted so the header lands in the slice belonging to the core that will process it.click to enlarge
From the paper: stock DPDK drops the packet header in a random LLC slice; CacheDirector steers it to the slice of the core that will process it.
EuroSys·2019

Make the Most out of Last Level Cache in Intel Processors

Work done in collaboration with Ericsson: CacheDirector unlocked a performance-enhancing feature that had existed in Intel processors for almost a decade, by placing data in the cache slice closest to the core that will use it.

Research

Projects

Wallenberg Scholar·2025 – 2029

(unlimited) ChatGPT for every child

The goal of my Wallenberg Scholar Project is to build a substantially more energy efficient platform for AI inferencing. The project runs from 2025 until 2029 and is titled “Sustainable and Adaptive Inferencing for Democratizing AI” (project blog link). An interview about the project is also available.

Our first paper shows that it is possible to efficiently extract programming-language-specific sub-models using appropriate calibration datasets while maintaining acceptable accuracy w.r.t. full models.

Which form of communication should Large Language Models (LLMs) use when they are collaboratively working on a problem, for example, one or two models processing the context and another model answering a question without seeing the context itself: plain text, hidden state, or some other way? In our ICLR 2026 paper we propose and evaluate an approach called KVComm that uses carefully selected KV pairs computed during self-attention for this purpose. Our KV selection strategy is based on attention importance scores and a Gaussian prior. KVComm reduces the computation costs by 2.5x to 6x relative to textual approaches, and enables up to a 3x reduction in communication relative to approaches that transmit the entire set of KV pairs.

VR SFL & WASP·ongoing

ML for systems, systems for ML

My recent focus is on using machine learning for systems, and building systems for machine learning. One key example is our Swedish Research Council (VR) project on Scalable Federated Learning (SFL). This project aims to develop a highly scalable, flexible, extensible, distributed federated machine learning approach that can directly benefit public health and wellness. In our CFD paper we demonstrate our ability to perform dropout on image recognition models using coding theory (e.g., using Gold codes), resulting in more than 2X network bandwidth savings when used for Federated Learning. Our FMM-head work shows the benefit of taking the underlying model of the heart (via Frequency Modulated Möbius waves) into account when performing ECG anomaly detection. Our model achieves up to 0.31 increase in area under the ROC curve (AUROC) when compared to the state of the art models. Moreover, the processing time of our model is four orders of magnitude lower than solving an optimization problem to obtain the same parameters, thus making it suitable for real-time ECG parameter extraction and anomaly detection. Our paper at STACOM demonstrates a potential for removing a large number of leads (more than half!) during ECG Imaging.

In the domain of optimization, our DeepGANTT IPSN '23 paper demonstrates our ability to apply transformers to Graph Neural Networks (GNNs) for scaling up an IoT scheduling problem 10X beyond what a constraint optimization solver can solve in a reasonable time. The follow-on RobustGANTT journal article demonstrates that GNN-based models with Transformer-like architecture trained on small 10-node networks can robustly generalize to large-scale IoT deployments with up to 1000 nodes (i.e., 100x bigger than those encountered during training), achieving up to 2× resource savings in energy and spectrum utilization while maintaining consistent performance across diverse network topologies.

ERC Consolidator · ULTRA·2018 – 2024

10x more efficient Internet Services

In my 2018-2024 ERC Consolidator Project called ULTRA, we wanted to dramatically change the way Internet Services are constructed. In our SoCC 2018 paper, we present Kurma, our fast and accurate load balancer for geo-distributed storage systems. We have collaborated with Ericsson on our CacheDirector work published at EuroSys 2019. The work on Metron (NFV service chains at the true speed of the underlying hardware) has led to, and has inspired this project. Our CoNEXT 2019 paper called RSS++ shows how load-balancing with Receive Side Scaling (RSS) can be improved for large increases in efficiency. In our NSDI 2020 paper we introduced Cheetah, a new load balancer for solving the difficult challenge of remembering which server is serving which connection, without the tradeoff between uniform load balancing and efficiency. In our ASPLOS 2021 paper, we have shown that vertically integrating a network protocol stack enables a single CPU core to forward packets faster than 100 Gbps. More details are available at the PacketMill project page. The Metron journal article is now also available, and it shows how high performance NFV service chaining can be done even in the presence of blackboxes. Our NSDI 2022 paper Packet Order Matters shows a surprising result: deliberately delaying packets can improve the performance of backend servers by up to a factor of 2 (e.g., those used for Network Function Virtualization)! We show three different scenarios in which our Reframer can be deployed. Our final work in this project is FAJITA, which shows that a commodity server running a chain of stateful network functions can process more than 170 M packets per second (equivalent of 1.4 Tbps if payloads are stored in a disaggregated fashion as in our earlier Ribosome work [NSDI ’23]!).

In our OSDI 2020 paper on Assise, we provide a blueprint of how a next generation distributed file system should be built on top of NVRAM that is becoming widely available, and achieve large performance gains. Our LineFS paper (Best Paper award at SOSP '21) builds upon this work by offloading CPU-intensive tasks to a SmartNIC (BlueField-1 in our case) for about 80% performance improvement across the board. Our RedN NSDI 2022 paper shows another surprising result, namely that Remote Direct Memory Access (RDMA), as implemented in widely deployed RDMA Network Interface Cards, is Turing Complete! We leverage this finding to reduce the tail latency of services running on busy servers by 35x!

SSF Framework · TCC·2016 – 2022

Time-Critical Clouds

A major focus area for my research group was on Time-Critical Clouds, a 2016-2022 project supported by SSF (the Swedish Foundation for Strategic Research) with 27 M SEK (~2.7 M EUR). This was a joint effort with the Connected Intelligence group of RISE AB. Our first major contribution is a Eurosys 2017 paper (link to video and paper available here). In this work we reduce the tail latency in key-value stores by up to 1.9x by scheduling multiget requests more efficiently. We have also shown how to run NFV service chains at the true speed of the underlying hardware in our NSDI '18 paper. In our EuroSys 2019 paper we have unlocked a performance-enhancing feature that existed in Intel processors for almost a decade. In our USENIX ATC 2020 paper, we are reexamining Direct Cache Access (DCA) to optimize I/O intensive applications for multi-hundred-gigabit networks. In our PAM 2021 paper, we show that the forwarding throughput of the widely-deployed programmable Network Interface Cards (NICs) sharply degrades when i) the forwarding plane is updated and ii) packets match multiple forwarding tables in the NIC.

ERC Starting Grant · PROPHET·2010 – 2016

Simplifying the way networked systems are developed and deployed

We have concluded the work on the PROPHET ERC project (2010-2016), in which we aimed to dramatically change the way networked systems are developed and deployed. For example, we improved the performance of geo-replicated storage systems using GeoPerf [SOCC '15]. We have successfully applied software verification techniques to increase the reliability of Software-Defined Networks (SDN). Some of our key contributions to testing of OpenFlow networks are NICE [NSDI '12] and SOFT [CoNEXT '12]. We have identified serious issues in the interplay between the control and data planes in OpenFlow switches [PAM '15], and proposed an approach for verifying rule installation [CoNEXT '14] as well as fine-grained dynamic monitoring of switch dataplanes [CoNEXT '15]. Extended versions of these contributions are available as IEEE/ACM TON and Elsevier Computer Networks journal publications. My work in Wallenberg AI, Autonomous Systems and Software Program (WASP) as a WASP faculty (advising an industrial PhD student at Ericsson, Amir Roozbeh) is complementary to these efforts.

We have wrapped up our work in the BEhavioral-BAsed Forwarding (BEBA) Horizon2020 project (2014-2017) that aimed to reshape Software-Defined Networks. Our contributions are described in George Katsikas' licentiate thesis, and involve deep understanding and performance optimization of Network Functions Virtualization (NFV) service chains. Moreover, our work on Synthesized Network Functions demonstrates high throughput with low predictable latency on a single commodity server thanks to its highly synthesized code and request dispatching. The overall project was highlighted by the EU commission.

Complete record

All publications

Journal, conference and workshop publications with full author lists.

Conference and Workshop Publications

Service

Selected Recent Service

ERC Starting Grant 2023 PE6 Panel Chair
ERC Starting Grant 2021 PE6 Panel Chair
ERC Starting Grant 2019 PE6 Panel member
ERC Starting Grant 2017 PE6 Panel member

TPC Co-chair of SYSTOR 2023
TPC Co-chair of EuroSys 2020
TPC Co-chair of ICDCS 2018 "Cloud Computing and Data Centers"
TPC Co-chair of CoNEXT 2016

TPC Member for NSDI '27

TPC Member for NSDI '26, OSDI '26, SOSP '26
TPC Member for NSDI '25, OSDI '25, SIGCOMM '25
TPC Member for ASPLOS '24, OSDI '24, SIGCOMM '24
TPC Member for NSDI '23
TPC Member for ASPLOS '22, NSDI '22, OSDI '22, SYSTOR '22
TPC Member for NSDI '21, SOSP '21
TPC Member for NSDI '20
TPC Member for SIGCOMM '19, USENIX ATC '19, NSDI '19
TPC Member for Eurosys '18, EuroSys '17, CoNEXT '18, CoNEXT '17
TPC Member for OSDI '16, CoNEXT '15, SoCC '15, NSDI'15
Group

Students

I am actively advising several doctoral students at KTH:


Some of my students at KTH have already defended their licentiate theses (a degree half-way to the doctoral degree in Sweden):

My Full CV contains the list of Master projects that were supervised and/or examined by me:

Courses

Teaching

At KTH, I teach (or have taught):

About

Short biography

Dejan Kostic obtained his Ph.D. in Computer Science at the Duke University. He spent the last two years of his studies and a brief stay as a postdoctoral scholar at the University of California, San Diego. He received his Master of Science degree in Computer Science from the University of Texas at Dallas, and his Bachelor of Science degree in Computer Engineering and Information Technology from the University of Belgrade (ETF), Serbia.

From 2006 until 2012 he worked as a tenure-track Assistant Professor at the School of Computer and Communications Sciences at EPFL (Ecole Polytechnique Federale de Lausanne), Switzerland. From 2012 until June 2014, he worked at the IMDEA Networks Institute (Madrid, Spain) as a Research Associate Professor with tenure. He is a Professor of Internetworking at KTH since April 2014.

Recognition

  • 2024 — Named a Wallenberg Scholar (18 MSEK, 5 years)
  • 2022 — Community Award, USENIX NSDI
  • 2021 — Best Paper Award, ACM SOSP
  • 2017 — European Research Council (ERC) Consolidator Award
  • 2010 — European Research Council (ERC) Starting Investigator Award

Full CV (PDF)

Get in touch

Contact

Email & phone

d m k <at> k t h <dot> s e
Office phone: +46 8-790 42 65

Physical address

Prof. Dejan Kostic
KTH, School of EECS
Teknikringen 18
114 28 Stockholm

My office is #355 on the upper three floor of the building locally called “Sing-Sing”. The building has two entrances, and you will have to call me or email me to let you in. I recommend this entrance Google Maps (59.348630, 18.073859), Teknikringen 18, 114 28 Stockholm.

Mailing address

Not my physical address.

Prof. Dejan Kostic
KTH
School of EECS
Malvinas v 10
114 28 Stockholm
Sweden
Off duty

Personal

I love taking Stockholm Photos, and my larger portfolio is here: https://pixels.com/profiles/dejan-kostic?tab=artwork.
You can also follow me (dmkostic) on Instagram and Twitter. My LinkedIn profile is here.